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RF1K49156
Data Sheet January 2002
6.3A, 30V, 0.030 Ohm, Logic Level, Single N-Channel LittleFETTM Power MOSFET
This Single N-Channel power MOSFET is manufactured using an advanced MegaFET process. This process, which uses feature sizes approaching those of LSI integrated circuits, gives optimum utilization of silicon, resulting in outstanding performance. It was designed for use in applications such as switching regulators, switching converters, motor drivers, relay drivers, and low voltage bus switches. This product achieves full rated conduction at a gate bias in the 3V - 5V range, thereby facilitating true on-off power control directly from logic level (5V) integrated circuits. Formerly developmental type TA49156.
Features
* 6.3A, 30V * rDS(ON) = 0.030 * Temperature Compensating PSPICE(R) Model * On-Resistance vs Gate Drive Voltage Curves * Peak Current vs Pulse Width Curve * UIS Rating Curve * Related Literature - TB334 "Guidelines for Soldering Surface Mount Components to PC Boards"
Symbol
BRAND RF1K49156
SOURCE (2) DRAIN (7) NC (1) DRAIN (8)
Ordering Information
PART NUMBER RF1K49156 PACKAGE MS-012AA
NOTE: When ordering, use the entire part number. For ordering in tape and reel, add the suffix 96 to the part number, i.e., RF1K4915696.
SOURCE (3)
DRAIN (6)
GATE (4)
DRAIN (5)
Packaging
JEDEC MS-012AA
BRANDING DASH
5
1 2 3 4
(c)2002 Fairchild Semiconductor Corporation
RF1K49156 Rev. B
RF1K49156
Absolute Maximum Ratings
TA = 25oC Unless Otherwise Specified RF1K49156 30 30 10 6.3 Refer to Peak Current Curve Refer to UIS Curve 2 0.016 -55 to 150 300 260 UNITS V V V A
Drain to Source Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDSS Drain to Gate Voltage (RGS = 20k, Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .VDGR Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VGS Drain Current Continuous (Pulse width = 1s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .ID Pulsed (Figure 5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDM Pulsed Avalanche Rating (Figure 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EAS Power Dissipation TA = 25oC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PD Derate Above 25oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ, TSTG Maximum Temperature for Soldering Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TL Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Tpkg
W W/oC oC
oC oC
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE: 1. TJ = 25oC to 125oC.
Electrical Specifications
PARAMETER
TA = 25oC, Unless Otherwise Specified SYMBOL BVDSS VGS(TH) IDSS TEST CONDITIONS ID = 250A, VGS = 0V, (Figure 13) VGS = VDS, ID = 250A, (Figure 12) VDS = 30V, VGS = 0V VGS = 10V ID = 6.3A, VGS = 5V, (Figures 9, 11) VDD = 15V, ID 6.3A, RL = 2.38, VGS = 5V, RGS = 25 (Figure 10) TA = 25oC TA = 150oC MIN 30 1 VGS = 0V to 10V VGS = 0V to 5V VGS = 0V to 1V VDD = 24V, ID = 6.3A, RL = 3.81 (Figure 15) Pulse Width = 1s Device Mounted on FR-4 Material TYP 35 100 150 95 52 29 1.8 2030 625 105 MAX 2 1 50 100 0.030 165 300 65 37 2.3 62.5 UNITS V V A A nA ns ns ns ns ns ns nC nC nC pF pF pF
oC/W
Drain to Source Breakdown Voltage Gate Threshold Voltage Zero Gate Voltage Drain Current
Gate to Source Leakage Current Drain to Source On Resistance Turn-On Time Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Turn-Off Time Total Gate Charge Gate Charge at 5V Threshold Gate Charge Input Capacitance Output Capacitance Reverse Transfer Capacitance Thermal Resistance Junction to Ambient
IGSS rDS(ON) tON td(ON) tr td(OFF) tf tOFF Qg(TOT) Qg(5) Qg(TH) CISS COSS CRSS RJA
VDS = 25V, VGS = 0V, f = 1MHz (Figure 14)
Source to Drain Diode Specifications
PARAMETER Source to Drain Diode Voltage Reverse Recovery Time SYMBOL VSD trr TEST CONDITIONS ISD = 6.3A ISD = 6.3A, dISD/dt = 100A/s MIN TYP MAX 1.05 58 UNITS V ns
(c)2002 Fairchild Semiconductor Corporation
RF1K49156 Rev. B
RF1K49156 Typical Performance Curves
1.2 POWER DISSIPATION MULTIPLIER 1.0 ID, DRAIN CURRENT (A) 0 25 50 75 100 TA , AMBIENT TEMPERATURE (oC) 125 150 0.8 7 6 5 4 3 2 1 0 25
0.6 0.4
0.2 0
50
75 100 125 TA, AMBIENT TEMPERATURE (oC)
150
FIGURE 1. NORMALIZED POWER DISSIPATION vs AMBIENT TEMPERATURE
FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs AMBIENT TEMPERATURE
10
ZJA, NORMALIZED THERMAL IMPEDANCE
DUTY CYCLE - DESCENDING ORDER 0.5 0.2 0.1 0.05 1 0.02 0.01 PDM
t1 0.1 t2 NOTES: DUTY FACTOR: D = t1/t2 PEAK TJ = PDM x ZJA x RJA + TA 10-1 100 101 102 103
SINGLE PULSE 0.01 10-3 10-2
t, RECTANGULAR PULSE DURATION (s)
FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE
100
VDSS MAX = 30V ID, DRAIN CURRENT (A) 10
IDM, PEAK CURRENT CAPABILITY (A)
TJ = MAX RATED, TA = 25oC
200 100 VGS = 5V
FOR TEMPERATURES ABOVE 25oC DERATE PEAK CURRENT AS FOLLOWS: I
= I25
150 - TA 125 TA = 25oC
1
5ms 10ms 100ms
10
0.1 OPERATION IN THIS AREA MAY BE LIMITED BY rDS(ON) 0.01 0.1 1 10 VDS, DRAIN TO SOURCE VOLTAGE (V) 1s DC 100
TRANSCONDUCTANCE MAY LIMIT CURRENT IN THIS REGION 1 10-5
10-4
10-3 10-2 10-1 t, PULSE WIDTH (s)
100
101
FIGURE 4. FORWARD BIAS SAFE OPERATING AREA
FIGURE 5. PEAK CURRENT CAPABILITY
(c)2002 Fairchild Semiconductor Corporation
RF1K49156 Rev. B
RF1K49156 Typical Performance Curves
50 IAS, AVALANCHE CURRENT (A)
(Continued)
50 VGS = 10V VGS = 5V
STARTING TJ = 25oC 10 STARTING TJ = 150oC
ID, DRAIN CURRENT (A)
40
VGS = 4V
30 VGS = 3V 20 VGS = 2.5V 10 PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX TA = 25oC 0 1 2 3 4 VDS, DRAIN TO SOURCE VOLTAGE (V) 5
1 0.1
If R = 0 tAV = (L)(IAS)/(1.3*RATED BVDSS - VDD) If R 0 tAV = (L/R)ln[(IAS*R)/(1.3*RATED BVDSS - VDD) +1] 1 10 tAV, TIME IN AVALANCHE (ms) 100
0
NOTE: Refer to Fairchild Application Notes AN9321 and AN9322. FIGURE 6. UNCLAMPED INDUCTIVE SWITCHING CAPABILITY FIGURE 7. SATURATION CHARACTERISTICS
50 ID(ON), ON-STATE DRAIN CURRENT (A) -55oC 40
150oC
rDS(ON), ON-STATE RESISTANCE (m)
25oC
VDD = 15V
250 ID = 15A 200
PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX VDD = 15V
30
150
ID = 6.3A ID = 3.5A ID = 1.75A
20
100
10 PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX 0 0 1.5 3.0 4.5 6.0 VGS, GATE TO SOURCE VOLTAGE (V) 7.5
50
0 2.0
2.5
3.5 4.0 4.5 3.0 VGS, GATE TO SOURCE VOLTAGE (V)
5.0
FIGURE 8. TRANSFER CHARACTERISTICS
FIGURE 9. DRAIN TO SOURCE ON RESISTANCE vs GATE VOLTAGE AND DRAIN CURRENT
300 VDD = 15V, ID = 6.3A, RL= 2.38 250 SWITCHING TIME (ns) 200 150
tD(OFF) NORMALIZED ON RESISTANCE
2.0 PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX VGS = 5V, ID = 6.3A 1.5
tf
1.0
tr 100 tD(ON) 50 0 0 10 20 30 40 RGS, GATE TO SOURCE RESISTANCE () 50
0.5
0 -80
-40
0 40 80 120 TJ, JUNCTION TEMPERATURE (oC)
160
FIGURE 10. SWITCHING TIME vs GATE TO SOURCE RESISTANCE
FIGURE 11. NORMALIZED DRAIN TO SOURCE ON RESISTANCE vs JUNCTION TEMPERATURE
(c)2002 Fairchild Semiconductor Corporation
RF1K49156 Rev. B
RF1K49156 Typical Performance Curves
2.0 NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE VGS = VDS, ID = 250A NORMALIZED GATE THRESHOLD VOLTAGE 1.5
(Continued)
2.0 ID = 250A 1.5
1.0
1.0
0.5
0.5
0 -80
-40
0
40
80
120
160
0 -80
-40
TJ, JUNCTION TEMPERATURE (oC)
0 40 80 120 TJ , JUNCTION TEMPERATURE (oC)
160
FIGURE 12. NORMALIZED GATE THRESHOLD VOLTAGE vs JUNCTION TEMPERATURE
2500
FIGURE 13. NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE vs JUNCTION TEMPERATURE
30 VDS , DRAIN-SOURCE VOLTAGE (V) 5.00 VGS , GATE-SOURCE VOLTAGE (V)
CISS 2000 C, CAPACITANCE (pF) VGS = 0V, f = 1MHz CISS = CGS + CGD CRSS = CGD COSS = CDS + CGD
VDD = BVDSS 22.5
VDD = BVDSS 3.75
1500 COSS 1000
15
RL = 4.76 IG(REF) = 0.65mA VGS = 5V PLATEAU VOLTAGES IN DESCENDING ORDER: VDD = BVDSS VDD = 0.75 BVDSS VDD = 0.50 BVDSS VDD = 0.25 BVDSS I G ( REF ) 20 -----------------------I G ( ACT ) t, TIME (s) I G ( REF ) 80 -----------------------I G ( ACT )
2.50
7.5
1.25
500 CRSS 0 0 5 10 15 20 VDS, DRAIN TO SOURCE VOLTAGE (V) 25
0
0
NOTE: Refer to Fairchild Application Notes AN7254 and AN7260. FIGURE 14. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE FIGURE 15. NORMALIZED SWITCHING WAVEFORMS FOR CONSTANT GATE CURRENT
Test Circuits and Waveforms
VDS BVDSS L VARY tP TO OBTAIN REQUIRED PEAK IAS VGS DUT tP RG IAS VDD tP VDS VDD
+
0V
IAS 0.01
0 tAV
FIGURE 16. UNCLAMPED ENERGY TEST CIRCUIT
FIGURE 17. UNCLAMPED ENERGY WAVEFORMS
(c)2002 Fairchild Semiconductor Corporation
RF1K49156 Rev. B
RF1K49156 Test Circuits and Waveforms
(Continued)
tON td(ON) tr RL VDS
+
tOFF td(OFF) tf 90%
90%
RG DUT
-
VDD 0
10% 90%
10%
VGS VGS 0 10%
50% PULSE WIDTH
50%
FIGURE 18. SWITCHING TIME TEST CIRCUIT
FIGURE 19. RESISTIVE SWITCHING WAVEFORMS
CURRENT REGULATOR
VDS (ISOLATED SUPPLY) VDD VDS VGS = 10V Qg(5) D VGS VGS = 5V Qg(TOT)
12V BATTERY
0.2F
50k 0.3F
SAME TYPE AS DUT
G
DUT VGS = 1V 0 S Qg(TH) VDS ID CURRENT SAMPLING RESISTOR Ig(REF) 0
Ig(REF) 0 IG CURRENT SAMPLING RESISTOR
FIGURE 20. GATE CHARGE TEST CIRCUIT
FIGURE 21. GATE CHARGE WAVEFORMS
Soldering Precautions
The soldering process creates a considerable thermal stress on any semiconductor component. The melting temperature of solder is higher than the maximum rated temperature of the device. The amount of time the device is heated to a high temperature should be minimized to assure device reliability. Therefore, the following precautions should always be observed in order to minimize the thermal stress to which the devices are subjected. 1. Always preheat the device. 2. The delta temperature between the preheat and soldering should always be less than 100oC. Failure to preheat the device can result in excessive thermal stress which can damage the device. 3. The maximum temperature gradient should be less than 5oC per second when changing from preheating to soldering. 4. The peak temperature in the soldering process should be at least 30oC higher than the melting point of the solder chosen. 5. The maximum soldering temperature and time must not exceed 260oC for 10 seconds on the leads and case of the device. 6. After soldering is complete, the device should be allowed to cool naturally for at least three minutes, as forced cooling will increase the temperature gradient and may result in latent failure due to mechanical stress. 7. During cooling, mechanical stress or shock should be avoided.
(c)2002 Fairchild Semiconductor Corporation
RF1K49156 Rev. B
RF1K49156 PSPICE Electrical Model
SUBCKT RF1K49156 2 1 3 ;
CA 12 8 2.953e-9 CB 15 14 2.810e-9 CIN 6 8 1.925e-9 DBODY 7 5 DBDMOD DBREAK 5 11 DBKMOD DPLCAP 10 5 DPLCAPMOD EBREAK 11 7 17 18 35.64 EDS 14 8 5 8 1 EGS 13 8 6 8 1 ESG 6 10 6 8 1 EVTO 20 6 18 8 1 IT 8 17 1 LDRAIN 2 5 1e-9 LGATE 1 9 1.04e-9 LSOURCE 3 7 2.37e-10 MOS1 16 6 8 8 MOSMOD M = 0.99 MOS2 16 21 8 8 MOSMOD M = 0.01 RBREAK 17 18 RBKMOD 1 RDRAIN 5 16 RDSMOD 2.43e-3 RGATE 9 20 1.639 RIN 6 8 1e9 RLDRAIN 2 5 10 RLGATE 1 9 10.4 RLSOURCE 3 7 2.37 RSOURCE 8 7 RDSMOD 15.8e-3 RVTO 18 19 RVTOMOD 1 S1A S1B S2A S2B 6 12 13 8 S1AMOD 13 12 13 8 S1BMOD 6 15 14 13 S2AMOD 13 15 14 13 S2BMOD
GATE 1
rev 2/7/95
LDRAIN DPLCAP 10 RLDRAIN DBREAK RDRAIN 5 DRAIN 2
ESG + LGATE 9 EVTO 20 + 18 8
6 8 VTO + 6
11 16 EBREAK 17 18 21 MOS1 RIN CIN 8 RSOURCE MOS2
+
DBODY
RGATE RLGATE
LSOURCE 7 SOURCE 3 RLSOURCE
S1A 12 S1B CA + EGS 6 8 13 8 14 13
S2A 15 S2B 13 CB EDS + 14 5 8 17
RBREAK 18 RVTO IT 19 VBAT +
VBAT 8 19 DC 1 VTO 21 6 0.453 .MODEL DBDMOD D (IS = 1.80e-12 RS = 1.50e-2 TRS1 = 3.70e-3 TRS2 = -2.23e-5 CJO = 2.63e-9 TT = 2.44e-8) .MODEL DBKMOD D (RS = 4.15e-1 TRS1 = 6.50e-3 TRS2 = -3.80e-5) .MODEL DPLCAPMOD D (CJO = 5.25e-10 IS = 1e-30 N = 10) .MODEL MOSMOD NMOS (VTO = 1.92 KP = 136 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u) .MODEL RBKMOD RES (TC1 = 9.25e-4 TC2 = 5.61e-7) .MODEL RDSMOD RES (TC1 = 3.62e-3 TC2 = 1.03e-5) .MODEL RVTOMOD RES (TC1 = -1.85e-3 TC2 = -6.00e-6) .MODEL S1AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -4.55 VOFF= -2.55) .MODEL S1BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -2.55 VOFF= -4.55) .MODEL S2AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -1.25 VOFF= 3.75) .MODEL S2BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = 3.75 VOFF= -1.25) .ENDS NOTE: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991.
(c)2002 Fairchild Semiconductor Corporation
RF1K49156 Rev. B
TRADEMARKS
The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks.
ACExTM BottomlessTM CoolFETTM CROSSVOLTTM DenseTrenchTM DOMETM EcoSPARKTM E2CMOSTM EnSignaTM FACTTM FACT Quiet SeriesTM
DISCLAIMER
FAST (R) FASTrTM FRFETTM GlobalOptoisolatorTM GTOTM HiSeCTM ISOPLANARTM LittleFETTM MicroFETTM MicroPakTM MICROWIRETM
OPTOLOGICTM OPTOPLANARTM PACMANTM POPTM Power247TM PowerTrench (R) QFETTM QSTM QT OptoelectronicsTM Quiet SeriesTM SILENT SWITCHER (R)
SMART STARTTM STAR*POWERTM StealthTM SuperSOTTM-3 SuperSOTTM-6 SuperSOTTM-8 SyncFETTM TinyLogicTM TruTranslationTM UHCTM UltraFET (R)
VCXTM
STAR*POWER is used under license
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.
LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or 2. A critical component is any component of a life systems which, (a) are intended for surgical implant into support device or system whose failure to perform can the body, or (b) support or sustain life, or (c) whose be reasonably expected to cause the failure of the life failure to perform when properly used in accordance support device or system, or to affect its safety or with instructions for use provided in the labeling, can be effectiveness. reasonably expected to result in significant injury to the user. PRODUCT STATUS DEFINITIONS Definition of Terms Datasheet Identification Advance Information Product Status Formative or In Design Definition This datasheet contains the design specifications for product development. Specifications may change in any manner without notice. This datasheet contains preliminary data, and supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design.
Preliminary
First Production
No Identification Needed
Full Production
Obsolete
Not In Production
This datasheet contains specifications on a product that has been discontinued by Fairchild semiconductor. The datasheet is printed for reference information only.
Rev. H4

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